A modified ART 1 algorithm more suitable for VLSI implementations

Author(s): LinaresBarranco, B. | SerranoGotarredona, T. |

Year: 1996

Citation: NEURAL NETWORKS Volume: 9 Issue: 6 Pages: 1025-1043

Abstract: This paper presents a modification to the original ART 1 algorithm (Carpenter & Grossberg, 1987a, A massively parallel architecture for a self-organizing neural pattern recognition machine, Computer Vision, Graphics, and Image Processing, 37, 54-115) that is conceptually similar, can be implemented in hardware with less sophisticated building blocks, and maintains the computational capabilities of the originally proposed algorithm. This modified ART 1 algorithm (which we will call here ART 1(m)) is the result of hardware motivated simplifications investigated during the design of an actual ART 1 chip [Serrano-Gotarredona et al., 1994, Proc. 1994 IEEE Int. Conf. Neural Networks (Vol. 3, pp. 1912-1916); Serrano-Gotarredona & Linares-Barranco, 1996, IEEE Trans. VLSI Systems, (in press)]. The purpose of this paper is simply to justify theoretically that the modified algorithm preserves the computational properties of the original one and to study the difference in behavior between the two approaches.

Topics: Neural Hardware, Applications: Other, Models: ART 1,

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